In deep submicron IC technology, one of the main design challenges is the provision of metal interconnects that, although being located in close vicinity to neighboring metal interconnects, experience little detrimental influence, e.g. capacitive coupling, from their neighbors. Several solutions have been proposed. For instance, low-k materials have been introduced in the buried interconnect layers between the metal tracks of such layers to reduce the amount of capacitive coupling. Recently, proposals even include the replacement of the low-k material in such buried interconnect layers with air gaps to further reduce the capacitive coupling between neighboring interconnects. An example of the introduction of air gaps is for instance disclosed in “Advanced Cu interconnects using air gaps” by L. G. Gossett et al. in Microelectronic Engineering, 82 (2005), pages 321-332 and in “The evolution of multi-level air gap integration towards 32 nm node interconnects” by R. Daamen et al. in Microelectronic Engineering, 84 (2007), pages 2177-2183.
However, such measures are not appropriate for the uppermost interconnect layer because this layer is typically exposed to significant mechanical forces during the back-end processing steps in the IC manufacturing. This is for instance demonstrated in FIG. 1, which shows a cross-section of an integrated circuit. The substrate 100, which typically includes the semiconductor devices such as transistors, diodes and so on, is covered by a number of interconnect layers 120, each comprising patterned metal portions 125 separated by a suitable dielectric material. The interconnect layers 120 are typically separated by via layers 130, including vias 135 that interconnect metal portions 125 in different interconnect layers 120. The uppermost interconnect layer 140 is the interconnect layer that is closest to the bond pads 160 of the IC, which are typically embedded in a passivation layer 150. In FIG. 1, the uppermost interconnect layer 140 has a dielectric material portion 145 located underneath the bond pad 160. In FIG. 1, the bond pad 160 is shown with a metal cap 170.
Upon wire-bonding the bond pad 160, the mechanical forces on the bond pad 160 to ensure a good connection between the bond pad 160 and a wire (not shown) can cause damage to the dielectric material portion 145, e.g. delamination, cracking or even collapse of the interconnect layer 140. Similar mechanical forces may for instance be experienced during some packaging steps, e.g. molding. Such damage is likely to cause electrical failures within the IC at some point during its lifetime. For this reason, relatively brittle low-k materials are avoided in the uppermost interconnect layers of an IC. However, even more robust dielectric materials, e.g. SiO2, can still suffer damage when exposed to such mechanical forces.
A known solution is disclosed in FIG. 2, which shows a cross-section of another IC design. Here, the area 245 of the interconnect layer 140 under the bond pad 160 is filled with metal interconnect portions to ensure that the metal, which typically is more rigid than the dielectric material in the interconnect layer 140 in between the metal portions, absorbs most of the pressure forces exerted on the IC during subsequent process steps. However, the introduction of such a design rule significantly reduces the flexibility of the interconnect design, which may prohibit the adequate routing of the required interconnections in the design stage of the IC.